1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the invention relates to an electrostatic discharge (ESD) protection circuit device of a silicon-controlled rectifier (SCR) type, which has a metal-oxide-silicon field-effect transistor (MOSFET) as a trigger circuit and is used in a semiconductor integrated circuit.
2. Description of the Related Art
As is well known, it is essential to make practical use of an SCR to protect a semiconductor integrated circuit (or its internal circuit) from ESD. The SCR has the advantage that its on-resistance is extremely low. The SCR is thus suitable to protect a gate insulation film that is thinned by microfabrication of elements in the internal circuit.
On the other hand, the SCR has the disadvantage that its trigger voltage is high. The trigger voltage is called a breakdown voltage or a snapback voltage. In other words, it is an anode-to-cathode voltage generated when the SCR changes from off-state to on-state (when it is triggered). If the trigger voltage is high, the internal circuit of the semiconductor integrated circuit is easily subjected to electrostatic discharge damage. The reason is as follows. The application of an ESD surge causes a destructive stress to be applied to the gate insulation films of the elements in the internal circuit, or it causes the elements in the internal circuit to turn on earlier than the SCR and causes a destructive current to flow through a circuit board.
A number of techniques have been so far proposed to lower the trigger voltage of an SCR. For example, a prior art trigger circuit is roughly divided into two types: one using a breakdown current at a reverse-biased PN junction, and another using an on-current in a forward-biased active element.
The former trigger circuit has the advantages that its area is relatively narrow and its leakage current is small in normal circuit operation. However, it is difficult to control the breakdown voltage at the PN junction and drop the trigger voltage to a fixed level or lower.
The latter trigger circuit has the advantage that the trigger voltage can be controlled relatively easily. For example, the trigger voltage can easily be controlled by varying the number of diodes when a diode is used as an active element (see M. P. J. Mergens et al., “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxide,” in IEDM '03 Tech. Digest, pp. 21.3.1-21.3.4, 2003).
Considering an ideal diode, trigger voltage Vt1 is given by the following equation:Vt1=(n+1)Vbiwhere n is the number of diodes, and Vbi is a diffusion potential at the PN junction. Vbi indicates an almost constant value (about 0.8V) that does not rely upon any process conditions. Thus, the trigger voltage Vt1 takes on discontinuous values such as 1.6V, 2.4V and 3.2V.
In general, the trigger voltage Vt1 has to be controlled to fall within a range from not lower than a power supply voltage to not higher than a breakdown voltage of a gate insulation film. This range becomes narrower as the elements in an internal circuit are microfabricated. The device disclosed in the above publication, in which the trigger voltage Vt1 takes on discontinuous values only, is unsuitable to design an ESD protection circuit device.
If the number of diodes decreases to lower the trigger voltage Vt1, leakage current increases in normal circuit operation.
A method of using a MOSFET in a trigger circuit is proposed (see Jpn. Pat. Appln. KOKAI Publication No. 9-134997). According to this method, an on-current necessary for triggering an SCR is generated by increasing the gate voltage of the MOSFET using a resistance-capacitance coupling element. In this method, a trigger voltage can finely be adjusted by controlling the threshold voltage or dimension of the MOSFET.
In the above proposed method, the resistance-capacitance coupling element has the property of blocking a signal whose frequency is RC−1 or lower. If, therefore, a power line is connected to a terminal, the gate voltage of the MOSFET is 0V in normal circuit operation and thus leakage current is extremely small. Even though it is an input/output signal line that is connected to the terminal and the frequency of an input/output signal is higher than that (100 MHz or higher) of an ESD surge, the resistance-capacitance coupling element does not block the input/output signal. A large leakage current occurs accordingly. In order to prevent the ESD surge from attenuating, the time constant (RC product) of the resistance-capacitance coupling element has to be set to 10 ns or larger. To achieve this, a very large circuit area is required.
As described above, conventionally, an ESD protection circuit device that improves in controllability of trigger voltage and reduces in leakage current in normal circuit operation could not be decreased in size. It was therefore difficult to achieve a high-performance semiconductor integrated circuit inexpensively.